The present invention relates generally to programmable counters, i.e., frequency dividers, and, more specifically, to an arrangement and method for a fully synchronized frequency divider exhibiting a near 50% duty cycle output signal especially suited for use in phase locked loop (PLL) frequency synthesizers.
One application for PLL frequency synthesizers is in modern communications systems, which require more efficient use of the limited and congested radio spectrum. To achieve more efficient use of this limited congested spectrum, such systems are utilizing high-speed data and elaborate signalling schemes to achieve greater message signal throughput. Such high speed data and elaborate signalling schemes, however, demand greater performance from the transmitter designed into such two-way radios. That is, these radios are required to achieve phase-lock quickly and to maintain an accurate carrier frequency with low noise and minimal jitter.
Furthermore, in mobile, and particularly portable applications, it is desirable to configure the PLL frequency synthesizer with programmable counters/frequency dividers, which draw a minimum amount of current appropriate for the application. Particularly, the programmable counter should be configured in such a way as to allow the use of low speed, minimal current drain dividers where appropriate within the chain of cascaded dividers therein, and reserve the use of high-speed, high current drain dividers for the first, initial input stages.
In addition, and in conflict with the above requirements, such programmable counters/frequency dividers should have a synchronized output signal and synchronized data loading to alleviate frequency jitter, or phase noise, inherent in commonly-available programmable counters utilized in such applications. The above problems are particularly troublesome when attempting to design a frequency-agile PLL frequency synthesizer for use with a two-way radio transmitter and receiver that is suitable for handling voice and high-speed data over relatively narrow bandwidth radio channels that are spaced very close together.
In any event, certain programmable counters are known which merely address one of the previously-mentioned constraints.
One such type of known counter has a 50% duty cycle, but requires a prime factor of two that limits its usefulness to applications where the selected integer, or divisor, N, is even. Although such counters provide an exact 50% duty cycle, almost all PLL frequency synthesizer applications for two-way radios require that the programmed count, N, span a range of integers, including odd as well as even integers within the range.
A second known type of programmable counter provides a near 50% duty cycle, but cannot be synchronously changed from one count or program state, N.sub.1, to another program state, N.sub.2. The main disadvantage of utilizing this type of counter is that the programmed count, N, changes state dependent on internal gate delays and may not coincide with the optimum point in time at which the change of state should occur. Furthermore, the gate delays are highly dependent on environmental conditions, such as temperature.
A third known type of counter provides an output signal which is not synchronized to the clock, or input signal. Such synchronization, however, is essential for low noise, minimal frequency jitter operation.
In general, programmable counters/frequency dividers not providing a near 50% duty cycle output signal typically have a duty cycle equal to or less than 1/N, where N is the selected divisor. In addition, the duty cycle is limited in such counters by the internal gate delays. Hence, the disadvantage of utilizing this type of counter is that stages following this low-duty cycle counter must operate at near the same frequency as the input frequency, even though N may be large and the counter output frequency may be much less than the input frequency. Thus, it is clear that this general group of counters is unsuitable and must be avoided, since choosing a counter having a near 50% duty cycle output signal clearly alleviates this disadvantage.
Accordingly, there exists a need for a fully synchronized, programmable counter/frequency divider exhibiting a near 50% duty cycle output signal independent of N, having synchronized data loading of a binary-encoded integer as the programmed count, or divisor, N, and having an output signal synchronized to the input signal. Such need exists for many applications requiring a fast-locking, low-noise, frequency synthesizer.